The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a method and apparatus for rapid cool-down of annealed wafer for the manufacture of integrated circuits. Merely by way of example, the invention has been applied to spike anneals for source and drain dopant activation for the manufacture of integrated circuits. But it would be recognized that the invention has a much broader range of applicability.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in IC fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. An example of such a limit is the cool-down rate of annealed wafers used for the manufacture of integrated circuits.
Fabrication of custom integrated circuits using chip foundry services has evolved over the years. Fabless chip companies often design the custom integrated circuits. Such custom integrated circuits require a set of custom masks commonly called “reticles” to be manufactured. A chip foundry company called Semiconductor International Manufacturing Company (SMIC) of Shanghai, China is an example of a chip company that performs foundry services. Although fabless chip companies and foundry services have increased through the years, many limitations still exist. For example, the limited cool-down rate of annealed wafer cannot usually effectively control thermal budget of anneals. These and other limitations are described throughout the present specification and more particularly below.
FIG. 1 is a simplified diagram for wafer temperature during furnace anneal or rapid thermal anneal. During wafer anneals, the wafer temperature changes with time. During time period 110, the wafer temperature remains at the pre-anneal temperature. During time period 120, the wafer temperature increases from the pre-annealed temperature to the anneal temperature. During time period 130, the wafer temperature remains steady at the anneal temperature. During time period 140, the wafer temperature decreases from the anneal temperature to the post-anneal temperature. The post-anneal temperature usually equals the pre-anneal temperature. During time period 150, the wafer temperature remains at the post-anneal temperature. At a feature size of 0.35 μm, time period 130 is usually one or several minutes, and the anneal process is usually performed in a furnace. At a feature size between roughly 0.25 μm and 0.15 μm, time period 130 usually ranges from about 5 seconds to about 30 seconds. The anneal process is usually performed in a single furnace, and is called rapid thermal anneal. As shown in FIG. 1, the anneal contributes to the thermal budget in the amount represented by area 160. Area 160 is determined at least in part by the anneal temperature, the length of time period 130, the ramp-up rate during time period 120, and the ramp-down rate during time period 130. In order to reduce feature size, the thermal budget should usually be lowered.
From the above, it is seen that an improved technique for processing semiconductor devices is desired.